Synopsis

Keywords: Parallel Imaging, Cardiovascular, Accelerator, Real-time

GRAPPA is a cartesian pMRI method widely adopted for high-speed image reconstruction in many clinical applications e.g. real-time cardiac MRI. However, general-purpose computers have limited processing capabilities to address the computational complexity of GRAPPA in real-time MRI. Recently, multi-processor system-on-chip (MPSoC) has emerged as a potential candidate to meet the rising computational demands of GRAPPA for real-time image reconstruction. In this paper, design and implementation details of a novel MPSoC based GRAPPA accelerator i.e. SOC-GRAPPA are presented. The experimental results of 18-coil cardiac dataset show that the proposed accelerator is capable of reconstructing 30 frames/second in real-time cardiac MRI.

Introduction

GRAPPA is a pMRI algorithm that reconstructs the missing k-space data of each coil by linearly combining the acquired k-space data¹. GRAPPA interpolates the missing k-space data in two separate stages: (i) calibration and (ii) synthesis². During the calibration stage, GRAPPA weight sets (W) are calculated by using fully sampled auto-calibration signals (ACS) lines i.e. W= (SRC^H SRC)^-1 ×(SRC^H TRG). In the synthesis stage, sequential convolution operations are performed between the under-sampled k-space data and GRAPPA weight sets to generate the fully sampled k-space data i.e. ACQ ×W . Later on, the fully sampled k-space data is transformed into multi-coil images by applying the inverse Fourier transform³. The multi-coil images are then combined using their sum-of-squares to generate a composite solution image (Figure-1).
The computational complexity of GRAPPA reconstruction process rises exponentially with an increase in the GRAPPA configuration parameters ⁴. However, there exists an inherent parallelism in both the stages of GRAPPA reconstruction that can be exploited to lessen the computational cost. To fully exploit the fine-grained parallelism in GRAPPA reconstruction, an application-specific hardware (e.g. MPSoCs) can be a lucrative option due to its ability to exploit the fine-grain parallelism.
In this paper, MPSoC based accelerator for GRAPPA i.e. SOC-GRAPPA has been proposed for fast image reconstruction in real time MRI. The proposed SOC-GRAPPA has been implemented on Zynq Ultrascale+ MPSoC device i.e., ZCU102 which is equipped with quad-core A53 processing system (PS), embedded Graphical Processing Unit (GPU) and programmable logic (PL) ⁵. The processing capabilities of the target MPSoC device are employed to fully exploit the inherent parallelism in GRAPPA for real-time image reconstruction in cardiac MRI. The efficacy of the proposed SOC-GRAPPA is validated by conducting several experiments on 18-coil in-vivo cardiac dataset.

Methodology

The proposed SOC-GRAPPA is composed of four modules i.e. (i) calibration (CAL), (ii) synthesis (SYN), (iii) arbitration (ARB) and (iv) storage (STO) as shown in Figure-2 . The CAL is implemented on programmable logic (PL) of the target device i.e. ZCU102. In order to keep the design effort to minimal, Vivado HLS framework has been employed for the implementation of CAL module. Furthermore, compiler directives i.e. HLS UNROLL and HLS PIPELINE are incorporated in high-level design specifications of CAL module to exploit the inherent parallelism in calibration stage of GRAPPA. On the other hand, the SYN module has been implemented on the GPU of target device i.e. ZCU102 using OpenGL ES. The SYN module performs a convolution operation between GRAPPA weight sets (W) and the under-sampled k-space data (ACQ) in an iterative manner. However, each iteration of SYN is an independent operation which can be performed concurrently. In order to execute multiple iterations, parallel threads are spawned on the embedded GPU using OpenGL ES. The ARB module is implemented on on-chip quad-core A53 processor i.e. PS using C++. The ARB module performs logic arbitration and resource allocation of the proposed MPSoC based accelerator. Whereas, the STO module comprises of a high-speed DDR4-SDRAM to store k-space data.
The proposed SOC-GRAPPA starts its operation by extracting SRC and TRG matrices from STO module. After the extraction, ARB module triggers CAL module for the estimation of GRAPPA weight sets (W) on PL. Once GRAPPA weight sets (W) are estimated, ARB module triggers SYN module to interpolate the missing k-space data on the embedded GPU using multiple threads. Each thread submits the synthesized data on to the dedicated location of memory inside the STO module.
The efficacy of the proposed SOC-GRAPPA is evaluated by conducting a series of experiments on 18-coil cardiac dataset for various GRAPPA configuration settings (acceleration factor = 2, 4 and number of ACS lines=32). The MR data acquisition details and hardware platform specifications are presented in Table-1 and Table-2, respectively. The reconstruction time and accuracy of the proposed SOC-GRAPPA are compared with single-threaded and multi-threaded CPU-based counterparts.

Results and Discussion

The reconstruction times of proposed SoC-GRAPPA and CPU-based counterparts are presented in Table-3. Moreover, the visual quality of reconstructed images is compared with the fully sampled reference image as shown in Figure-3. The results presented in Table-3 and Figure-3 show that proposed SoC-GRAPPA is capable of reconstructing ~30 frames/second while maintaining visual quality of the reconstructed images.

Conclusion

In this paper, a novel MPSoC based accelerator for GRAPPA reconstruction i.e. SOC-GRAPPA has been designed with an aim to accelerate GRAPPA reconstruction while maintaining the optimal visual quality of reconstructed images. The proposed SOC-GRAPPA is capable of reconstructing up to 30 frames/second as compared to CPU-based counterparts which can only reconstruct 2 frames/second for a given GRAPPA reconstruction setting in our experiments.

Acknowledgements

No acknowledgement found.