Introduction

Parallel MRI (pMRI) methods allow faster data acquisitions using multiple receiver coils. However, data processing using multiplier receiver coils causes exponential growth in the reconstruction time of pMRI methods such as sensitivity encoding (SENSE)¹ and Generalize Auto calibrating Partial Parallel Acquisition (GRAPPA)². Recently, Eigen value methods such as principal component analysis (PCA)³ have been adopted to compress the multiple channel information into fewer receiver coils data while retaining the important information, thus significantly reducing computer memory requirements and reconstruction time for pMRI methods.
Singular Value Decomposition (SVD) of a matrix is a useful tool for dimension reduction using PCA⁴. SVD⁵ decomposes a given matrix (A_nxm) into three main components i.e. $$$A = U S V^T$$$ where, S is singular diagonal matrix containing eigen values; U and V are columns and rows orthogonal matrices containing the information of Eigen vectors. The time complexity of computing SVD of an n×m matrix is O(nm min(m, n))⁶;and for high rank data sets, SVD becomes computationally expensive. Moreover, SVD does not have independent operations which could be exploited using hardware or software solutions to speed the process of compression. In this work, an FPGA based accelerator for coil compression is designed which employs QR decomposition using modified Gram-Schmidt⁷ to obtain accurate information of the Eigen vectors required for data compression. QR decomposition⁸ procedure decomposes a given matrix (A_nxm) into two main components i.e. $$$A = QR$$$ where, Q is the orthogonal matrix and R is the upper triangular matrix. In modified Gram-Schmidt method, all the column vectors of matrix (A_nxm) are modified to be orthogonal to the first column vector of marix (A_nxm)for faster computation as it orthogonalizes the column vectors simultaneously⁹. The proposed accelerator exploits the inherent parallelism in QR decomposition and works in coordination with an on-chip processor to perform image reconstruction using multiple receiver coil data. It is demonstrated that coil compression using the proposed accelerator can be highly effective for GRAPPA and SENSE methods in terms of reconstruction time and quality.

Method

In this work, an FPGA based accelerator for channel compression is proposed to accelerate GRAPPA and SENSE reconstruction without compromising the image quality as shown in Fig. 3. The proposed accelerator obtains accurate information of Eigen vectors based on QR decomposition using modified Gram–Schmidt method which decomposes the given matrix (Anxm) into an orthogonal matrix(Qnxm) and an upper triangular matrix (Rmxm)10; the pseudo code is shown in Fig. 1.
Rmxm and (Rmxm)T compute the orthonormal matrices (Unxn) and (Vmxm) by orthogonalizing all the column vectors with respect to the first column vectors of each matrix. Unxn and Vmxm are columns and rows of Eigen vectors to calculate the Eigen values of receiver coil data matrices. Eigen vectors calculate the dimensionally reduced matrix contains the essential and compressed information with fewer coils as shown in Fig. 2. The reduced coil data from channel compression algorithm works in coordination with an on-chip ARM processor11 using AXI4-stream-interconnect12 for efficient GRAPPA and SENSE reconstruction.
For implementation of the proposed accelerator, High-Level Synthesis(HLS) framework provided by VIVADO HLS tool13 is used. HLS framework provides flexibility in terms of architectural optimization for different configuration settings(SENSE and GRAPPA). The design flow of the proposed accelerator is:
(i) Generation of high precision source code of the coil compression algorithm bases on C/C++ language using floating-point data type in compliance with VIVADO HLS design constraints. As a result, VIVADO HLS tool automatically generates the RTL code of the 32-bit single-precision floating-point FPGA-based accelerator for channel compression.
(ii)The optimization pragmas such as “HLS PIPELINE”(pipelines the data processing) and “HLS UNROLL"(unrolls loops to provide data level parallelism in algorithm) are used to generate RTL. RTL is simulated and verified through C/C++ test bench based RTL wrappers. Finally, RTL design of the channel compression accelerator consisting of IO ports is packaged as HLS intellectual property(IP) block referred as “Channel Compression Accelerator”. The proposed IP is well equipped with the required interfaces to work in coordination with on-chip ARM processor where GRAPPA and SENSE reconstructions are performed on the compressed data.
(iii) Finally, the bit file of 32-bit floating-point Channel Compression Accelerator is generated for implementation on Xilinx FPGA development board ZCU102 that contains an on-chip ARM Cortex®-A53 64-bit quad-core processor.

Result and Discussion

The experiments are performed on a 30 channel cardiac data set using various configuration settings as shown in Table 1. For a fair comparison, the performance of GRAPPA and SENSE reconstructions with FPGA based channel compression is evaluated against single-core and multi-core CPU. The results show that the proposed accelerator speeds up the reconstruction times (GRAPPA and SENSE) up to 15x with acceptable SNR as shown in Table 1. The proposed accelerator utilizes less resources to reduce receiver coil data and reduces computer memory requirements without degrading image quality as shown in Fig. 3.

Conclusion

The proposed work presents a novel FPGA based accelerator for channel compression which exploits the inherent parallelism in the QR decomposition. The results show that coil compression using the proposed accelerator offers speed up in the reconstruction time with for GRAPPA and SENSE methods with no compromise on image quality.

References

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