Synopsis

To lower the entry barrier for MRI system development, an open source PXIe platform consisting of IP for peripheral boards, an associated linux device driver and example system controller and peripheral boards were developed. The design was capable of performing system controller initiated DMA transfers in both directions with a maximum block size of 8MB. The hardware design was greatly simplified by mounting FPGA modules from Avnet onto custom PXIe compatible carrier boards. The modules from Avnet contained a System on a Chip device from Xilinx consisting of a dual core ARM processor and FPGA fabric.

Purpose

Method

The entry barrier for MRI system development is very high due to the complexity and the high speed interconnect requirements. Often, a modular approach is taken either using a high cost standard commercial parallel or serial backplane system or developing a simple custom parallel backplane [1,2]. PXIe [3] is a good backplane option as the clock rate of the PCIe serial data is way beyond any NMR receiver channel and being a standard allows one to make use of modules provided by many vendors. However, until now, PXIe platforms and modules are usually expensive and contain proprietary Intellectual Property (IP) so system developers have no choice but to purchase a complete vendor platform or if developing own hardware still have to pay for IP. This, as well as the system complexity, is a potential barrier to a lot university based researchers who want to develop their own MRI system hardware.

With the release of high performance integrated processor/FPGA devices from vendors such as Xilinx [4] and the availability of open source Linux operating systems has made it significantly easier to develop complex systems. The Xilinx ZYNQ series are a single chip device that contain a dual core ARM processor, FPGA fabric and dedicated PCIe peripheral units. This device combined with Linux is an elegant solution for implementing a PXIe system controller. The ZYNQ device, or just one of the newer FPGA devices with PCIe peripheral units can be used as the basis for the required transceiver or gradient controller modules. Now to implement a PXIe solution one still needs to develop the PCIe communications hardware for the modules as well as a device driver for the operating system. There are several vendors offering FPGA IP and device drivers but at a significant cost. The focus of this work was to develop freely available IP, a device driver and example designs so that other researchers can easily build their own MRI or other instrumentation systems.

To make it even easier to develop systems, some component distributers such as Avnet [5] have developed plug in System On Module (SOM) solutions that are basically a small system board that contains either a ZYNQ device or just a FPGA, some memory, communications interfaces as well as a connector to interface with a host board. In our case, this host board is either a system controller board or a module and plugs directly into a standard PXIe chassis. This therefore allows the rapid development of Instrumentation systems.

Implementation

A PXIe system controller board (Figure 1) with a 1 lane PCIe rootport was developed that used a PicoZed, ZYNQ7045 SOM from Avnet with a GB Ethernet interface and USB interface. A custom PXIe compatible RF transceiver peripheral board (Figure 2) with 1 lane PCIe was also developed but using a XILINX SPARTAN 6 FPGA device mounted directly on the peripheral board. The system controller and peripheral boards were inserted into a National Instruments [6] PXIe chassis. IP for the peripheral board and an associated linux device driver was developed to allow system controller initiated DMA transfers in both directions with a maximum block size of 8MB. The device driver was also expended to support multiple peripheral modules. The device driver, FPGA IP and PCB schematics are available via GitHub.

The next step already in development is a system controller board using a lower cost PicoZed, ZYNQ7015 SOM, GB Ethernet interface, USB interface, 4 lane PCIe rootport, with a PCIe switch to drive 4 banks as per the PXIe standard. Also to be developed in the near future are, backplanes, a system timing board and a full MRI implementation.

Conclusion

Acknowledgements

References