Matrix gradient coils were recently proposed for encoding showing their potential to offer high flexibility in generating dynamic customized spatial encoding magnetic fields1-3. The generation of specific spatial encoding magnetic fields may be very flexible if each coil element is driven by its own amplifier. However, to drive a high number of coil elements, such a system might not be feasible due to the high costs of an increased number of commercial gradient amplifiers. Moreover, typical commercial gradient amplifiers are designed for high inductive loads. A single coil element of a matrix coil cannot be driven directly because of the very low inductance; an additional inductive load is often needed in series with the coil element to match the output requirements of a commercial gradient amplifier. Additionally, if the number of coil elements is increased, the current requirement for each gradient power amplifier would be reduced, while maintaining the same current density inside a matrix coil. Here we present the design and implementation of a prototype amplifier, capable of 100A/100V with the requirement of low cost.Figure 1 shows the block diagram of the gradient amplifier. The amplifier consists of a controller, an H-bridge circuit and a ripple cancellation filter. The controller contains a fiber-optic receiver, a field-programmable gate array (FPGA), a digital to analog converter (DAC), a voltage-controlled pulse width modulator (PWM), an analog Proportional-Integral (PI) controller and an error amplifier. The amplifier was designed using a standard constant current source topology, where the current demanded by the DAC is compared with the sampled current through the coil via a current sensor (LA 100-P, LEM, Swiss). Current waveform signals are sent in real-time via a commercial high speed digital IO board (PCIe-6536, National Instruments) to the amplifier. The optical fiber is used to achieve galvanic isolation between the amplifier and the PCIe-6536 board. The frequency of the PWM (LTC6992-2, Linear Technology) was set to 100 kHz to achieve a high bandwidth of the amplifier. A phase lock loop (PLL) including a phase detector and a PI controller was developed to synchronize multiple amplifiers with an external 100 kHz reference clock and compensate the frequency error of the analog PWM chip. To drive different loads, a digital potentiometer and octal single pole, single throw (SPST) switches are connected to different capacitors to tune the proportional and integral parameters. The H-Bridge circuit contains two transformer-isolated half-bridge drivers with a 4 A output capability (ADuM4223, Analog Devices) and four 150A/150V MOSFETs (IXFN180N15P, IXYS). The ripple cancellation filter was implemented based on the design of Sabate et al.4. A prototype gradient power amplifier was constructed with water cooling, shown in Figure 2. Different loads (422uH, 123uH and 12uH) were successfully tested with continuous current up to 100 A for up to 1 min. The bandwidth and peak ripple current of the amplifier is approximately 10 kHz and 300 mA, respectively. The total cost is less than 1 000 €. Figures 3 and 4 show the currents and voltages of a trapezoid and triangle waveform, respectively, for the 123uH load. Due to the lack of a feedforward module, the controller can’t adjust the current very fast during the transition period as shown in Figures 3 and 4; this might degrade the image quality. The stable time of the PLL module is in the range of a few tens of microseconds, this might limit use of the amplifier for some sequences. To improve the performance of the amplifier, a full digital controller including a feedforward module, a feedback module and an interleaved PWM module will be implemented.