N-path frequency mixers for ultra-high density receive arrays
Michael Twieg1, Soumyajit Mandal1, and Mark A Griswold1,2

1Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, United States, 2Radiology, Case Western Reserve University, Cleveland, OH, United States

Synopsis

Dense MRI receiver arrays face challenges associated with RF cabling, power consumption, and space required by on-coil RF LNAs. On-coil frequency mixers and ADCs have been proposed as solutions to these challenges. Here we propose the use of passive N-path mixers implemented in CMOS for on-coil frequency conversion. We demonstrate a prototype fabricated in a 0.5µm CMOS process, and compare its measured and simulated performance. We also show simulations of a similar design in 65nm CMOS with greatly improved performance. The improved version may handle multiple RF channels on a single chip, and eliminates the need for RF LNAs entirely.

Purpose

Receive arrays are trending towards higher channel counts in order to increase coverage while maintaining good SNR and enable acceleration with parallel imaging. However, increased density poses engineering challenges, including the physical size of on-coil LNAs and the routing of RF cables for each channel. Prior work has explored frequency mixing on-coil for frequency domain multiplexing [1]–[3], but the use of discrete frequency mixers is problematic due to their poor gain and noise figure. Direct digitization of the RF with high speed ADCs has also been explored [4], [5], but the lack of frequency translation requires high sampling rates and power dissipation. Here we propose the use of receivers based on passive N-path mixers implemented in CMOS for on-coil frequency conversion.

Methods

N-path receiver: Our method is heavily based on work by Andrews and Molnar [6]–[8], which demonstrates a mixer-first tunable receiver core based on N-path mixers and baseband low noise amplifiers integrated on a single CMOS die (TSMC 65nm). We used the NCSU Cadence design kit to design a similar receiver core (see Fig. 1) for operation at FRF=64MHz. The design was fabricated with the MOSIS educational program (ON Semiconductor C5N 0.5μm process). The receiver is fed with a 252MHz reference LO, which is split into eight non-overlapping pulses at 63MHz that drive the switches of an eight-path passive mixer. The result is eight intermediate frequency signals at FIF=1MHz with interleaved phase, which feed four differential IF LNAs. The gain of the LNAs and the dead time of the LO pulses were adjustable with a serial peripheral interface (SPI). The mixer sampling capacitors are also implemented on-chip. The gain, single sideband noise figure, IP1dB, and power consumption of the mixer are simulated and measured experimentally. Dynamic range (DR) is calculated assuming a channel bandwidth of 200kHz. Layout area and power consumption do not include the LO divider, bypass capacitors, or bondpads.

Packaging and external circuitry: The IC itself is 1.5x1.5mm, but was packaged in a large DIP-40 carrier, as provided at no cost from MOSIS. The packaged mixer is shown on a test PCB in Fig 2. External amplifiers and filters were used to combine the eight IF outputs into a single IF port [6] for noise figure measurements. The reference LO was derived from an ADF4351 frequency synthesizer (Analog Devices).

65nm design simulation: A schematic-level design of an N=16 receiver core was created with the UMC 65nm foundry design kit. The smaller feature size and wider variety of devices in this process allow large improvements in performance and density.

Results

Table I summarizes the results of the simulations for both 0.5μm and 65nm designs, and the experimental results for the 0.5µm design. The measurements were performed with the LNAs configured for maximum and minimum gain. The external IF combination circuitry had an overall gain of -2dB and an image rejection ratio of -30dB. The NFSSB was measured experimentally using the gain method [9], and was measured at the output of the IF combination chain. In addition to the power required by the mixer core (including the LNAs and mixer drivers), the 0.5μm design required 30mW for the LO divider.

Discussion and conclusions

In its present state, the 0.5μm mixer does not offer significant advantages over on-coil RF LNAs due to its large package size, high power consumption, and high NF. However, we demonstrate that these parameters can be accurately predicted with simulation. By following a similar design methodology with the 65nm process, we predict an improved NFSSB near 0.5dB while requiring a fraction of the power and area. Such a low NF makes the use of RF LNAs unnecessary; a matched coil can be fed directly to the mixer input, allowing for the mixer’s wideband and tunable properties to be exploited. Ultimately we envision multiple N-path receiver cores implemented on a single chip, as shown in Fig. 3. Each of the M coil channels feeds a mixer core, all of which share a common LO bus. The N interleaved IF ports of each receiver core would be reduced to quadrature outputs, which are sampled by matched integrated ADCs. The M results are digitally downconverted (DDC) then combined and serialized over a single digital link. This would allow for on-coil digitization with relatively low power compared to direct sampling of the RF with a single ADC. M channels could be supported with a single cable carrying DC power and the reference LO, while a fiber optic or wireless link could transmit the digital output back to the scanner.

Acknowledgements

This work was supported by Siemens healthcare. We also thank the MOSIS MEP and the NCSU CDK project.

References

[1] W. He, X. Qin, R. Jiejing, and L. Gengying, “Four-channel magnetic resonance imaging receiver using frequency domain multiplexing,” Review of Scientific Instruments, vol. 78, no. 1, p. 015102, 2007.

[2] M. J. Riffe, M. D. Twieg, N. Gudino, C. J. Blumenthal, J. A. Heilman, and M. A. Griswold, “Identification and mitigation of interference sources present in SSB-based wireless MRI receiver arrays: Interference Sources in SSB-Based MRI Receiver Arrays,” Magnetic Resonance in Medicine, vol. 70, no. 6, pp. 1775–1786, Dec. 2013.

[3] R. H. Buchwald, “MR receiver assembly having readout cables capable of multiple channel transmissions,” US7449886 B2, 11-Nov-2008.

[4] F. V. Liere, “MRI system with direct digital receiver using resampling,” US8049505 B2, 01-Nov-2011. [5] J. Reber, D. O. Brunner, T. Schmid, U. Moser, B. E. Dietrich, C. Barmet, and K. P. Pruessmann, “In-Bore Broadband Array Receivers with Optical Transmission,” presented at the ISMRM, Milan, IT, 2014.

[6] C. Andrews and A. C. Molnar, “A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2696–2708, Dec. 2010. [7] C. Andrews and A. C. Molnar, “Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 12, pp. 3092–3103, Dec. 2010.

[8] A. Molnar and C. Andrews, “Impedance, filtering and noise in n-phase passive CMOS mixers,” 2012, pp. 1–8.

[9] “Three Methods of Noise Figure Measurement,” Maxim Integrated. [Online]. Available: https://www.maximintegrated.com/en/app-notes/index.mvp/id/2875. [Accessed: 22-Oct-2015].

Figures

Figure 1: Diagram of the N=8 receiver core, as well as the interleaved LO divider. The LO divider takes a reference LO (with frequency FLO∙N/2) and divides it into N non-overlapping pulses with interleaved phase, each of which feeds a mixer path. RF source impedance is assumed to be 50Ω.


Figure 2: Test PCB with optional IF combination circuitry, consisting of harmonic recombination amplifiers and a polyphase filter combiner. The IC is powered with 5V, was can be configured via SPI by an Arduino Uno (not shown).


Table 1: Performance of various designs at FRF=64MHz, FIF=1MHz.


Figure 3: Conceptual multichannel receiver architecture without RF LNAs. The IF quadrature outputs of each channel are sampled by separate ADCs. A digital downconverter (DDC) combines IF quadrature data into complex baseband data. A serializer combines all channels to be sent to the host over a common media.



Proc. Intl. Soc. Mag. Reson. Med. 24 (2016)
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