Receive arrays are trending towards higher channel counts in order to increase coverage while maintaining good SNR and enable acceleration with parallel imaging. However, increased density poses engineering challenges, including the physical size of on-coil LNAs and the routing of RF cables for each channel. Prior work has explored frequency mixing on-coil for frequency domain multiplexing [1]–[3], but the use of discrete frequency mixers is problematic due to their poor gain and noise figure. Direct digitization of the RF with high speed ADCs has also been explored [4], [5], but the lack of frequency translation requires high sampling rates and power dissipation. Here we propose the use of receivers based on passive N-path mixers implemented in CMOS for on-coil frequency conversion.

N-path receiver: Our method is heavily based on work by Andrews and Molnar [6]–[8], which demonstrates a mixer-first tunable receiver core based on N-path mixers and baseband low noise amplifiers integrated on a single CMOS die (TSMC 65nm). We used the NCSU Cadence design kit to design a similar receiver core (see Fig. 1) for operation at F_RF=64MHz. The design was fabricated with the MOSIS educational program (ON Semiconductor C5N 0.5μm process). The receiver is fed with a 252MHz reference LO, which is split into eight non-overlapping pulses at 63MHz that drive the switches of an eight-path passive mixer. The result is eight intermediate frequency signals at F_IF=1MHz with interleaved phase, which feed four differential IF LNAs. The gain of the LNAs and the dead time of the LO pulses were adjustable with a serial peripheral interface (SPI). The mixer sampling capacitors are also implemented on-chip. The gain, single sideband noise figure, IP1dB, and power consumption of the mixer are simulated and measured experimentally. Dynamic range (DR) is calculated assuming a channel bandwidth of 200kHz. Layout area and power consumption do not include the LO divider, bypass capacitors, or bondpads.

Packaging and external circuitry: The IC itself is 1.5x1.5mm, but was packaged in a large DIP-40 carrier, as provided at no cost from MOSIS. The packaged mixer is shown on a test PCB in Fig 2. External amplifiers and filters were used to combine the eight IF outputs into a single IF port [6] for noise figure measurements. The reference LO was derived from an ADF4351 frequency synthesizer (Analog Devices).

65nm design simulation: A schematic-level design of an N=16 receiver core was created with the UMC 65nm foundry design kit. The smaller feature size and wider variety of devices in this process allow large improvements in performance and density.

Table I summarizes the results of the simulations for both 0.5μm and 65nm designs, and the experimental results for the 0.5µm design. The measurements were performed with the LNAs configured for maximum and minimum gain. The external IF combination circuitry had an overall gain of -2dB and an image rejection ratio of -30dB. The NF_SSB was measured experimentally using the gain method [9], and was measured at the output of the IF combination chain. In addition to the power required by the mixer core (including the LNAs and mixer drivers), the 0.5μm design required 30mW for the LO divider.In its present state, the 0.5μm mixer does not offer significant advantages over on-coil RF LNAs due to its large package size, high power consumption, and high NF. However, we demonstrate that these parameters can be accurately predicted with simulation. By following a similar design methodology with the 65nm process, we predict an improved NF_SSB near 0.5dB while requiring a fraction of the power and area. Such a low NF makes the use of RF LNAs unnecessary; a matched coil can be fed directly to the mixer input, allowing for the mixer’s wideband and tunable properties to be exploited. Ultimately we envision multiple N-path receiver cores implemented on a single chip, as shown in Fig. 3. Each of the M coil channels feeds a mixer core, all of which share a common LO bus. The N interleaved IF ports of each receiver core would be reduced to quadrature outputs, which are sampled by matched integrated ADCs. The M results are digitally downconverted (DDC) then combined and serialized over a single digital link. This would allow for on-coil digitization with relatively low power compared to direct sampling of the RF with a single ADC. M channels could be supported with a single cable carrying DC power and the reference LO, while a fiber optic or wireless link could transmit the digital output back to the scanner.